Method of making multilevel MEMS structures
US6861363B2 · kind B2 · utility
8Cited by
5References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2002 |
| Grant date | Mar 1, 2005 |
| Priority date | — |
| Expiry date | Jan 31, 2023 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C1/00626
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Multi-levels are etched into silicon. The levels are etched through a combination of crosslinking photoresist, multiple photoresist patterning and development, wet etching and/or dry-etching. RIE, DRIE, and other etch techniques can be used during different steps. The multilevel structure may thereby be produced at commercially acceptable production rates allowing the method of the present application to be used in volume production of multilevel structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.