Barrier region and method for wafer scale package (WCSP) devices
US6861721B1 · kind B1 · utility
0Cited by
7References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2003 |
| Grant date | Mar 1, 2005 |
| Priority date | — |
| Expiry date | Dec 8, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F77/93
Abstract
A barrier region provided in the active surface of a wafer-level chip scale package device or chip (WCSP device or chip) to substantially reduce the amount of photon-generated substrate current that reaches active circuitry within the active area of the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.