Method and apparatus for performing power routing on a voltage island within an integrated circuit chip
US6861753B1 · kind B1 · utility
2Cited by
0References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2003 |
| Grant date | Mar 1, 2005 |
| Priority date | — |
| Expiry date | Oct 9, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for performing power routing on a voltage island within an integrated circuit chip is disclosed. A first power grid is generated for a voltage island on metal levels 1 to N−1. Then, a second power grid is generated on metal levels N and above. A bounding region of the second robust power grid is determined. Finally, the shortest distance connections from a set of power sources is routed to the second power grid.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.