Flip chip with novel power and ground arrangement
US6861762B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 1, 2002 |
| Grant date | Mar 1, 2005 |
| Priority date | — |
| Expiry date | Aug 21, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A flip chip assembly comprising a semiconductor die having a core area and a periphery area. The periphery area including an ESD structure. The semiconductor die includes at least one power conductor to supply power between the core area and the periphery. A substrate is coupled to the semiconductor die via a plurality of electrically conductive bumps. A first connection circuit is located within the semiconductor die core area to couple power between the substrate and the semiconductor die power conductor. An electrically conductive bump provides a connection between the first connection circuit and the substrate. The ESD structure is coupled to the first connection circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.