Clock deskew protocol using a delay-locked loop
US6861886B1 · kind B1 · utility
33Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 21, 2003 |
| Grant date | Mar 1, 2005 |
| Priority date | — |
| Expiry date | May 26, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data/clock deskewing methodology uses a delay-locked loop (DLL) circuit. The DLL circuit generates a number of clock phases in response to an input clock, where each clock phase is delayed relative to the input clock signal. The clock phases are used to sample data from a data line. The sampled data is checked against a preamble pattern (a sequence of known data). A digital deskew control block selects one of the clock phases after analyzing the results of preamble pattern check such that subsequently received data is sampled with the appropriately selected clock phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.