Clocked-scan flip-flop for multi-threshold voltage CMOS circuit
US6861887B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2002 |
| Grant date | Mar 1, 2005 |
| Priority date | — |
| Expiry date | Dec 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/012
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A clocked-scan flip-flop for multi-threshold CMOS (MTCMOS) is provided. The clocked-scan flip-flop includes a first switching unit which switches normal data that are input from the outside and outputs the data; a second switching unit which switches scan data that are input from the outside and outputs the data; a latch unit which latches the data input from the first switching unit or the second switching unit; and a clock input unit which controls the switching operations of the first and second switching units according to the result of a predetermined operation on a clock signal and a scan clock signal that are input from the outside. The clocked-scan flip-flop has the characteristics of a complementary pass-transistor (CP) flip-flop, that is, low power consumption and high performance. Also, the clocked-scan flip-flop provides a full-scale scan function for test purposes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.