Sub-harmonic mixer
US6861891B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 25, 2003 |
| Grant date | Mar 1, 2005 |
| Priority date | — |
| Expiry date | Nov 25, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D7/125
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A sub-harmonic mixer comprises two field effect transistors in which the sources of the transistors are connected together and the drains of the transistors are connected together. The mixer includes signal generating means for generating a local oscillator (LO) signal coupled to the gate of one of the FETs. Circuit means is provided for maintaining the potential of the gate of the other FET at a substantially constant value relative to the local oscillator signal applied to the gate of the driven FET, and the FET's are arranged to permit the local oscillator signal applied to gate of the driven FET to drive a voltage across the gate-source of both FET's. An input and output port is coupled to the drains for receiving input signals for the mixer and outputting output signals from the mixer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.