Static random access memory
US6862207B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2002 |
| Grant date | Mar 1, 2005 |
| Priority date | — |
| Expiry date | Nov 18, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for a four transistor SRAM comprising an array or block of cells. Each cell comprises a pair of pass transistors and a pair of pull-down transistors. In one embodiment of the invention, when the SRAM block is in a standby mode, the difference between the voltage at the gate and the voltage at the source of each pass transistor is greater than 0, and less than the threshold voltage of the pass transistor. In one embodiment of the invention a ground connection of the memory cell is switched such that when the SRAM block is in the standby mode, the ground connection is a virtual ground connection and when the SRAM block is in an active mode the ground connection is a global ground connection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.