Zipper type VDSL system
US6862261B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2000 |
| Grant date | Mar 1, 2005 |
| Priority date | — |
| Expiry date | Dec 19, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L5/023
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Disclosed is a zipper type Very high bit-rate Digital Subscriber Line (VDSL) system which comprises a transmitter including an inverse fast Fourier transformer for performing an inverse fast Fourier transform on input data, and a cyclic extension adder for adding a cyclic extension for each symbol to the data output from the inverse fast Fourier transformer and outputting the data to a transmission channel; and a receiver including a cyclic extension remover for removing the cyclic extension from the data received through the transmission channel, and a fast Fourier transformer for performing a fast Fourier transform on the data output from the cyclic extension remover. The cyclic extension adder copies a first predetermined number of data starting from the leading part of the input symbol data received from the inverse fast Fourier transformer into a first cyclic suffix for removing interference between symbols and maintaining orthogonality between sub-carriers; adds the first cyclic suffix to the end of the symbol data; copies a second predetermined number of data subsequent to the first predetermined number of data into a second cyclic suffix for maintaining orthogonality betwee…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.