Method and apparatus for managing the configuration and functionality of a semiconductor design
US6862563B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 1999 |
| Grant date | Mar 1, 2005 |
| Priority date | — |
| Expiry date | Oct 14, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of managing the configuration, design parameters, and functionality of an integrated circuit (IC) design using a hardware description language (HDL). Instructions can be added, subtracted, or generated by the designer interactively during the design process, and customized HDL descriptions of the IC design are generated through the use of scripts based on the user-edited instruction set and inputs. The customized HDL description can then be used as the basis for generating “makefiles” for purposes of simulation and/or logic level synthesis. The method further affords the ability to generate an HDL model of a complete device, such as a microprocessor or DSP. A computer program implementing the aforementioned method and a hardware system for running the computer program are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.