Methodology of generating antenna effect models for library/IP in VLSI physical design
US6862723B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2002 |
| Grant date | Mar 1, 2005 |
| Priority date | — |
| Expiry date | Apr 29, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A new method to route a metal line in the layout of an integrated circuit device is achieved. The method comprises providing a layout for an integrated circuit device comprising an array of placed standard cells. Contact/via layer polygons are placed for coupling the standard cells. A line is routed in a metal layer. An antenna effect value is calculated for the line using parameters previously determined from the layout of each the standard cell. The parameters comprise gate area, diode area, metal area, and contact/via area coupled to the line. The gate area, the diode area, the metal area, and the contact/via area are segregated by metal level. The steps of routing and calculating are repeated if the antenna effect value exceeds a specified value. A method to extract parameters is disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.