Hybrid bulk/silicon-on-insulator multiprocessors
US6864524B2 · kind B2 · utility
17Cited by
7References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2004 |
| Grant date | Mar 8, 2005 |
| Priority date | — |
| Expiry date | Feb 24, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor integrated circuit is disclosed. A preferred embodiment of a multiprocessor chip has microprocessors formed on silicon-on-insulator regions and dynamic random access memory level-2cache memories or level-3 cache memories formed on bulk regions of the chip. A preferred embodiment includes a redundant architecture having a signal bus for coupling the microprocessors to the level-2 or level-3 cache memories in which the signal bus includes a programmable selector circuit for bypassing defective microprocessors or defective level-2 or level-3 cache memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.