Reconfigurable memory architecture
US6864716B2 · kind B2 · utility
3Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2003 |
| Grant date | Mar 8, 2005 |
| Priority date | — |
| Expiry date | Sep 9, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/025
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A pre-diffused high density array of core memory cells is provided in a metal programmable device. The peripheral logic is made up of gate array cells in the metal programmable device. The peripheral logic may be configured to access the core memory cells as various memory types, widths, depths, and other configurations. If the entire memory is not needed, then the unused memory cells can be used as logic gates. The application-specific circuit, including peripheral logic, memory interface logic, and memory configuration is programmed with a metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.