Flip-flop circuit with reduced power consumption
US6864732B2 · kind B2 · utility
14Cited by
3References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 18, 2002 |
| Grant date | Mar 8, 2005 |
| Priority date | — |
| Expiry date | Nov 18, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/012
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low power flip-flop is disclosed. The number of transistors which are coupled to the clock signal is reduced by more than half when compared with known flip-flop designs. The flip-flop comprises a pair of clocked transistors forming a pass gate and a plurality of inverters coupled thereto. By reducing the number of clock signal connections needed for reliable operation, the present invention reduces the power consumed by the flip-flop when operating at typical levels of activity by up to 70%.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.