Stabilization technique for phase-locked frequency synthesizers
US6864753B2 · kind B2 · utility
9Cited by
4References
21Claims
0Family size
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Key dates
| Filing date | Jan 29, 2003 |
| Grant date | Mar 8, 2005 |
| Priority date | — |
| Expiry date | Jan 29, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/099
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A stabilization technique that relaxes the tradeoff between the settling speed and the magnitude of output sidebands in phase-locked frequency synthesizers. The method introduces a zero in the open-loop transfer function through the use of a discrete-time delay element, thereby obviating the need for resistors in the loop filter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.