Graphics data synchronization with multiple data paths in a graphics accelerator
US6864892B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2002 |
| Grant date | Mar 8, 2005 |
| Priority date | — |
| Expiry date | Dec 21, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/005
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A system and method for preserving the order of data items through a divergence-and-reconvergence of two or more paths in a hardware device. A host processor may write a first token to a first path in the hardware device. A convergence unit in the hardware device may receive and store the first token in a synchronization register. The host processor may poll the synchronization register to determine when the first token arrives in the synchronization register. In response to determining that the first token has arrived in the synchronization register, the host processor may safely write a sequence of one or more data items to a second path in the hardware device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.