Row redundancy in a content addressable memory device
US6865098B1 · kind B1 · utility
36Cited by
4References
50Claims
0Family size
Assignee
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Key dates
| Filing date | May 30, 2003 |
| Grant date | Mar 8, 2005 |
| Priority date | — |
| Expiry date | Jun 5, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A content addressable memory (CAM) has a main array including a plurality of rows of CAM cells, one or more spare rows of CAM cells selectable to functionally replace defective rows of CAM cells in the main array, and a control circuit for disabling the defective rows by writing predetermined data to the defective rows of CAM cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.