Method and apparatus for testing a serial transmitter circuit
US6865222B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 22, 2000 |
| Grant date | Mar 8, 2005 |
| Priority date | — |
| Expiry date | Aug 14, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/24
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (12) contains a serializing transmitter, including a phase locked loop (31) that supplies seven clocks (41) with different phases to a serializer circuit (32). The serializer circuit accepts 7-bit words at a parallel input (42), and outputs these words serially in an end-to-end manner on a twisted pair (17), as a clock signal. The serializer circuit also accepts 7-bit words on a further parallel input (43), and transmits them serially in an end-to-end manner on a twisted pair (18), as serialized data. The integrated circuit also includes a built-in self-test circuit (33), which can supply test information to the two parallel inputs of the serializer circuit, and which can monitor the two twisted pairs while the serializer circuit operates at high data rates typical of normal operation, in order to detect any errors introduced by the serializer circuit. The self-test circuit produces a single digital output (48) to indicate whether an error has been detected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.