System and method for dynamic power management using data buffer levels
US6865653B2 · kind B2 · utility
19Cited by
4References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2001 |
| Grant date | Mar 8, 2005 |
| Priority date | — |
| Expiry date | Aug 5, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power management system for digital circuitry uses data buffer monitoring to determine appropriate processor clock speed or voltage. This allows a processor to be switched from a low power state to a high power state when a monitored data buffer level feeding data to a power intensive application is greater than a second memory buffer level. The processor is switched from a high power state to a low power state when the monitored data buffer level is less than a first memory buffer level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.