Control processor dynamically loading shadow instruction register associated with memory entry of coprocessor in flexible coupling mode
US6865663B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 23, 2001 |
| Grant date | Mar 8, 2005 |
| Priority date | — |
| Expiry date | Dec 5, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3656
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system are described which provide flexible coupling between a coprocessor and a control processor. The system includes a coprocessor and a system control bus connecting the coprocessor with the control processor. The coprocessor has two modes of access. In the first mode of access, the coprocessor retrieves an instruction stored in instruction memory and, in the second mode of access, the coprocessor retrieves an instruction from the control processor. The system control bus provides a path for loading an instruction to the coprocessor's shadow instruction register. The coprocessor, upon retrieving an entry in its instruction memory associated with the shadow instruction resigter, determines whether to load the instruction as an address in its program counter or to load the contents of the shadow instruction register into the instruction decode register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.