Method and apparatus for improved memory core testing
US6865701B1 · kind B1 · utility
17Cited by
15References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2001 |
| Grant date | Mar 8, 2005 |
| Priority date | — |
| Expiry date | Jul 29, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory unit is described that has a controller coupled to a memory core through an interface circuit. The interface circuit has a test data input that receives test data from the controller. The interface circuit also has a system data input that receives data from a system. The interface circuit has a data output that is coupled to a data input of the memory core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.