Diamond metal-filled patterns achieving low parasitic coupling capacitance
US6867127B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 19, 2002 |
| Grant date | Mar 15, 2005 |
| Priority date | — |
| Expiry date | Dec 19, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are methods and composition for forming diamond metal-filled patterns above an integrated circuit substrate. A metal layer is formed above the integrated circuit substrate, which is then patterned such that a metal line is created. A plurality of diamond-shaped metal regions are then formed at least one of above and adjacent to the metal line formed on the integrated circuit substrate such that the density of metal on the integrated circuit substrate is greater than a specified density, thereby ensuring that a surface of dielectric formed above the metal line remains substantially planar after application of CMP to the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.