Semiconductor packaging
US6867499B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 2, 2000 |
| Grant date | Mar 15, 2005 |
| Priority date | — |
| Expiry date | Oct 2, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic component and a method for making an electronic component are disclosed. The electronic component has a silicon package. The silicon package has a recess formed thereon in which a conductive region is placed. A bare die electronic device is disposed in the recess. The device has a top, a bottom, sides and a plurality of terminals, including a non-top terminal. The non-top terminal is electrically coupled to the conductive region. The electronic component is constructed by first creating a recess in a silicon wafer to a depth substantially equal to the first dimension of the bare die electronic device. A conductive material is applied to the recess. The electronic device is inserted into the recess so that the bottom terminal is coupled to the conductive material. A dielectric or other planarizing material is applied into the recess. Top and bottom contacts are then applied to form the electronic component so that it may be used as a ball grid array package. The top contact is electrically coupled to the top terminal of the electronic device and the bottom contact is coupled electrically to the conductive material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.