Membrane test method and apparatus for integrated circuit testing
US6867607B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2002 |
| Grant date | Mar 15, 2005 |
| Priority date | — |
| Expiry date | Jul 8, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R1/0735
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The specification describes a flexible membrane test apparatus and test method for high-speed IC chips. The method and apparatus rely on locating the reference components of the test circuit very close to the contact pads of the IC chip under test. This is achieved in one embodiment by locating those components adjacent to the flexible membrane. In another embodiment, the reference components may be attached to the membrane itself, so the length of the runners connecting the contact points of the tester and the critical reference components is optimally reduced. In yet a further embodiment, the entire test circuit, in the form of an IC test chip, is located on the membrane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.