Interlace overlap pixel design for high sensitivity CMOS image sensors
US6867806B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 1999 |
| Grant date | Mar 15, 2005 |
| Priority date | — |
| Expiry date | Nov 4, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/76
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In a CMOS-type image sensor, a plurality of pairs of light-detecting elements (LDEs) are arranged in rows and columns to generate analog signals proportional to the intensity of light impinging on respective one of the LDEs. First and second photo sensing means in each pair of LDEs are coupled in parallel, in the column direction, at a floating sensing point through first turn-on means. The first and second photo sensing means in adjacent pairs of LDEs are coupled in parallel in the column direction through second turn-on means. The first turn-on means are enabled by first control lines and the second turn-on means are enabled by second control lines coupled thereto, respectively. Analog signals acquired in the first and second photo sensing means of one pair or of adjacent pairs are present at the floating sensing point in response to the enabling of the first or second control lines, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.