Stacked-NMOS-triggered SCR device for ESD-protection

US6867957B1 · kind B1 · utility

Assignee

• Pericom Semiconductor Corporation · US

Inventors

• Paul C. F. Tong · San Jose, US
• Ming-Dou Ker · Hsinchu, TW
• Ping Ping Xu · San Jose, US

Key dates

• Filing date: Oct 9, 2002
• Grant date: Mar 15, 2005
• Expiry date: Jun 12, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/811

Abstract

Transistors with very thin gate oxides are protected against oxide failure by cascading two or more transistors in series between an output pad and ground. The intermediate source/drain node between the two cascaded transistors is usually floating during an ESD test, delaying snapback turn-on of a parasitic lateral NPN transistor. This intermediate node is used to drive the gate of an upper trigger transistor. A lower trigger transistor has a gate node that is charged by the ESD pulse on the pad through a coupling capacitor. When the coupled ESD pulse turns on the trigger transistors, the trigger transistors turn on a silicon-controlled rectifier (SCR) that is integrated with the trigger transistors.