Synchronous semiconductor memory device having a desired-speed test mode
US6868020B2 · kind B2 · utility
7Cited by
3References
4Claims
0Family size
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Inventor
Key dates
| Filing date | Jul 8, 2003 |
| Grant date | Mar 15, 2005 |
| Priority date | — |
| Expiry date | Jul 8, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronous DRAM has a test mode wherein a specified external signal is input to a command decoder of the DRAM. The command decoder generates a plurality of internal commands including activating signal for selecting a word line, write signal, precharge signal, another activating signal and read signal at consecutive timings which do not depend on an external clock signal. A low-speed memory tester can be used for testing the high-speed synchronous DRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.