Method and apparatus for checking read errors with two cyclic redundancy check stages
US6868517B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2002 |
| Grant date | Mar 15, 2005 |
| Priority date | — |
| Expiry date | Sep 23, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/29
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for detecting errors in data read from a data storage medium include an error correction step/device which receives at least one of (i) data and (ii) data with errors, from the data storage medium, and outputs an error sequence in a first order in the case where data with errors is received. A first CRC step/device receives the at least one of (i) data and (ii) data with errors from the data storage medium, and outputs a CRC checksum in a second order different from said first order. A second CRC step/device receives both the error sequence and the CRC checksum, and outputs another CRC checksum indicative of whether the correction device or step has generated a correct error sequence. Preferably, a first CRC is coupled parallel to a Reed-Soloman decoder, and a second CRC is coupled in series with the first CRC and so as to receive the output of the R-S decoder. The second CRC will thus be able to detect errors in the output of the R-S decoder, and provide an error signal which will cause the erroneous data to be reread.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.