Scalable hierarchical I/O line structure for a semiconductor memory device
US6870205B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2003 |
| Grant date | Mar 22, 2005 |
| Priority date | — |
| Expiry date | Jan 7, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device having a hierarchical I/O line structure is provided. The semiconductor memory array includes a memory cell array which is divided into a plurality of sub-arrays by sub-word line driver areas and bit line sense amplifier areas; local input/output (I/O) lines which are arranged in the bit line sense amplifier areas; and global I/O lines which are arranged in the sub-word line driver areas, wherein at least one end of each of the local I/O lines is formed in a bit line sense amplifier area. The semiconductor memory device may also have a dummy bit line sense amplifier area capable of dividing local I/O lines in a bit line sense amplifier area, and can reduce the number of sub-word line driver areas such that the chip size can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.