High speed I/O pad and pad/cell interconnection for flip chips
US6870273B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2003 |
| Grant date | Mar 22, 2005 |
| Priority date | — |
| Expiry date | Apr 29, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Gridded I/O pads for flip-chip packages in which a coaxial-like solder bump pad configuration is used in which the I/O pads closest to the signal or bump pad are power or ground pads. The ground pads surrounding the signal pad form a coaxial-like pad configuration for impedance matching at the transition from die to package substrate. The ground pads surrounding the signal pad may be connected by a metal trace to form a ground pad ring. The invention employs conductor-backed ground coplanar waveguides (GCPW), which match impedance at connections between I/O cells and signal pads to enhance signal transmission, avoid reflection and leakage, and provide superior electromagnetic shielding. The present invention also supports high quantities of I/Os for a given die size, and supports flexible power and ground placement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.