Programmable logic devices with integrated standard-cell logic blocks

US6870395B2 · kind B2 · utility

Assignee

• Lattice Semiconductor Corporation · US

Inventors

• John Schadt · Bethlehem, US
• William B. Andrews · Emmaus, US
• Zheng Chen · Macungie, US
• Anthony K. Myers · Hamburg, US
• David A. Rhein · Birmingham, US
• Warren L. Ziegenfus · Emmaus, US
• Fulong Zhang · Emmaus, US
• Ming H. Ding · San Jose, US
• Larry R. Fenstermaker · Nazareth, US

Key dates

• Filing date: Mar 18, 2003
• Grant date: Mar 22, 2005
• Expiry date: May 19, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K19/17796
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A programmable logic device (PLD) with a programmable logic core, block memory, and I/O circuitry has one or more blocks of standard-cell logic (SLBs) that are integrated into the PLD design to enable each SLB to be programmably connected to any one or more of the programmable core, the block memory, and/or the I/O circuitry. The addition of standard-cell-based functional blocks creates a PLD with increased overall logic density, a net smaller die size per function, lowered cost, and improvements to both power and performance characteristics relative to equivalent conventional PLDs, such as FPGAs.