Memory system including a memory device having a controlled output driver characteristic
US6870419B1 · kind B1 · utility
34Cited by
55References
42Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2003 |
| Grant date | Mar 22, 2005 |
| Priority date | — |
| Expiry date | Jul 23, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0298
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.