Output stage, amplifier and associated method for limiting an amplifier output
US6870426B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2003 |
| Grant date | Mar 22, 2005 |
| Priority date | — |
| Expiry date | Sep 17, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/3076
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method for implementing an amplifier capable of limiting or clamping an amplifier output signal is described. A clamp buffer and an input buffer cooperate to bias an output circuit according to the relative level of a clamp signal and an input signal. In a normal mode, in which the input signal has a first relationship with the clamp signal, the output circuit provides an output signal based on the input signal. In a clamping mode, in which the input signal has a second relationship with the clamp signal, the output circuit provides an output signal based on the clamp signal, which can be substantially fixed. The clamp signal can be set by the user to establish a desired clamping range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.