Row redundancy memory repair scheme with shift to eliminate timing penalty
US6870782B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2003 |
| Grant date | Mar 22, 2005 |
| Priority date | — |
| Expiry date | Jun 4, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory having built-in self repair with row shifting is provided. The rows in the memory are divided into smaller row groups and a bad row group is repaired with a redundant row group. Each row group receives a row select signal, which is fed into a shift circuit for the row group and a shift circuit for an adjacent row group. A shift circuit is provided for the redundant row group and the shift circuit for the redundant row group receives the row select signal for only the adjacent row group. If a bad row group is detected, then starting with the row group furthest from the redundant row group, the shift circuit for each row group before the bad row group is deactivated. The row group select signal and word line signal for the bad row group are disabled. The shift circuit for the bad row group and the shift circuit for each row group after the bad row group are activated. Therefore, the bad row group is disabled and the redundant row group fills the void.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.