Method and apparatus for automatically configuring and/or inserting chip resources for manufacturing tests
US6871154B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2003 |
| Grant date | Mar 22, 2005 |
| Priority date | — |
| Expiry date | Jul 31, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/267
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present invention is directed to a method and an apparatus for automatically configuring and/or inserting chip resources for manufacturing tests. A maximum test configuration (“test backplane”) for all IP blocks is created and loaded into a tool suite. When a user issues a request to consume some IP blocks, the request may be checked for legality within the “test backplane”. If a test resource (IP block) is not available for activation, then either the test resource may not be activated or the conflicting resource problem must be resolved so that the test resource may be activated. This may avoid late design surprises. The resources on the platform may already have test structures associated with them. All of these test structures may be associated with the “test backplane”. These pre-exiting test structures may then be connected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.