Method and arrangement in a stack having a memory segmented into data groups having a plurality of elements
US6871256B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 2002 |
| Grant date | Mar 22, 2005 |
| Priority date | — |
| Expiry date | Oct 20, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a data memory arrangement for a microprocessor system, in which the data memory is designed as a group memory composed of element memories in which data are storable in data groups having a plurality of elements under a group address in each instance, in order to make available a stack in which the memory space can be optimally utilized without the occurrence of memory gaps, the use is proposed of at least one memory pointer that has a group address component and an element address component. The stack memory can be operated with data words whose width is smaller than the data group width, without unutilized memory areas occurring in the stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.