Bent gate transistor modeling
US6871333B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2002 |
| Grant date | Mar 22, 2005 |
| Priority date | — |
| Expiry date | Jun 13, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of characterizing a total width and an overall effective length for a bent gate. The bent gate is divided into logical portions, and each of the logical portions is designated as one of a bent portion, a corner portion, and a straight portion. A corner portion gate width and a corner portion effective length are computed for each of the logical portions designated as a corner portion. Similarly, a bent portion gate width and a bent portion effective length are computed for each of the logical portions designated as a bent portion. Likewise, a straight portion gate width and a straight portion effective length are computed for each of the logical portions designated as a straight portion. The total width of the bent gate is computed from the corner portion gate width, the bent portion gate width, and the straight portion gate width. Similarly, the overall effective length of the bent gate is computed from the corner portion effective length, the bent portion effective length, and the straight portion effective length.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.