Method of forming an integrated circuit thin film resistor
US6872655B2 · kind B2 · utility
8Cited by
2References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2003 |
| Grant date | Mar 29, 2005 |
| Priority date | — |
| Expiry date | Feb 4, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01C7/006
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A thin film resistor structure (75) is formed on a dielectric layer (60). A capping layer (90) is formed above said thin film resistor structure (75) and vias (110) are formed in the capping layer (90) using a two step etching process comprising of a dry etch process and a wet etch process. Conductive layers (120) are formed in the vias and form electrical contacts to the thin film resistor structure (75).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.