Multi-step tungsten etchback process to preserve barrier integrity in an integrated circuit structure
US6872668B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2000 |
| Grant date | Mar 29, 2005 |
| Priority date | — |
| Expiry date | Jul 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32115
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved method is provided for etching back a tungsten layer that overlies a titanium nitride adhesion layer on a semiconductor structure. This method includes the steps of: (1) performing a first plasma etchback of the tungsten layer for a first predetermined time period, such that a thin layer of tungsten remains over the adhesion layer at the end of the first plasma etchback, (2) actively or passively cooling the resulting semiconductor structure to a temperature of 35° C. or lower, and then (3) performing a second plasma etchback of the tungsten layer until an endpoint is detected, thereby exposing the adhesion layer. Cooling the semiconductor structure prior to the second plasma etchback ensures that the titanium nitride adhesion layer is at a relatively low temperature during the second plasma etchback. The titanium nitride adhesion layer etches significantly slower at lower temperatures, thereby making it easier to stop the second plasma etchback on the adhesion layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.