Reduced size plate layer improves misalignments for CUB DRAM
US6873001B1 · kind B1 · utility
2Cited by
1References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 10, 1999 |
| Grant date | Mar 29, 2005 |
| Priority date | — |
| Expiry date | Mar 13, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
Abstract
In a DRAM array using a capacitor-under-bitline (CUB) layout, the plate layer of the capacitor is significantly reduced in area to reduce misalignments in connections between the bitline and the underlying transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.