Integrated circuit testing device and a method of use therefor
US6873146B2 · kind B2 · utility
5Cited by
5References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 12, 2003 |
| Grant date | Mar 29, 2005 |
| Priority date | — |
| Expiry date | Mar 12, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31723
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present invention provides an integrated circuit testing device 200 and a method of using the same. In one particular embodiment, the integrated circuit testing device may include a first circuit layer 220 located over a semiconductor substrate 210, wherein the first circuit layer 220 has a second circuit layer 230 located thereover. The integrated circuit testing device 200 of the same embodiment may further include a signal bond pad 240 selectively connectable to each of the first and second circuit layers 220, 230 to test at least one device on each of the first and second circuit layers 220, 230.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.