Logic array devices having complex macro-cell architecture and methods facilitating use of same
US6873185B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 4, 2002 |
| Grant date | Mar 29, 2005 |
| Priority date | — |
| Expiry date | Dec 19, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17796
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Logic array devices having complex macro-cell architecture and methods facilitating use of same. A semiconductor device comprising an array of logic cells and programmable metal includes gate structures that are pre-wired, where, inputs and/or outputs are available for routing in programmable metal, possibly as part of a hybrid process. The device can also include selectable, in-line inverters, which can share the input/output tracks with logic inputs. A bubble-pushing algorithm can take advantage of the selectable in-line inverters to reduce the number of inverters in a design. In some embodiments, an embedded clock line is common to a plurality of logic cells. The clock line is terminated in a clock cell, which can include test logic, so that a clock group is formed. Flexibility to power down cells, or groups of cells can be provided by power traces with programmable connections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.