Slew rate control of output drivers using FETs with different threshold voltages
US6873196B2 · kind B2 · utility
2Cited by
8References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 2, 2001 |
| Grant date | Mar 29, 2005 |
| Priority date | — |
| Expiry date | Aug 2, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/164
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A novel method and apparatus is presented for reducing the slew rate of transition edges of a digital signal on a node of an integrated circuit by connecting transistors with differing threshold voltages between the node and a voltage source and driving the gates of these transistors with the same driving signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.