Power down system and method for integrated circuits
US6873215B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2003 |
| Grant date | Mar 29, 2005 |
| Priority date | — |
| Expiry date | Sep 14, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3228
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power down system and method for an integrated circuit that enables a power down mode to be maintained for a predetermined time is described herein. The power down system comprises an oscillator, a low power oscillator and an oscillator control circuit controlling both the oscillator and the low power oscillator. The oscillator control circuit including at least one real time counter. The oscillator control circuit being so configured that the oscillator is energized when said oscillator control circuit is in a normal mode and that, when a power down signal is received: a) the oscillator control circuit measures an oscillation frequency of the low power oscillator, b) the oscillator control circuit uses the measured oscillation frequency of the low power oscillator to set the real time counter so as to maintain the power down mode for the predetermined time, c) the oscillator control circuit turns off the oscillator and uses the low power oscillator for the duration of the power down.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.