Integrated circuit device with a built-in detecting circuit for detecting maximum memory access time of an embedded memory
US6873557B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2003 |
| Grant date | Mar 29, 2005 |
| Priority date | — |
| Expiry date | Jun 19, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/104
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device includes an embedded memory, a built-in self-test (BIST) circuit, an access time measuring circuit, and a built-in detecting circuit. The BIST circuit is coupled electrically to the memory, and is operable so as to perform consecutive test operations upon addressable memory locations of the memory. The access time measuring circuit is coupled electrically to the memory and the BIST circuit, and is operable so as to generate an access time signal corresponding to access time of one of the memory locations that is currently being tested by the BIST circuit. The detecting circuit is coupled electrically to the measuring circuit, monitors a maximum value of the access time signals generated by the measuring circuit during the consecutive test operations, and outputs a maximum access time signal upon completion of the consecutive test operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.