Adaptive computing engine with dataflow graph based sequencing in reconfigurable mini-matrices of composite functional blocks
US6874079B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 25, 2001 |
| Grant date | Mar 29, 2005 |
| Priority date | — |
| Expiry date | Nov 30, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/321
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of a method and system for digital signal processing within an adaptive computing engine are described. These aspects include a mini-matrix, the mini-matrix comprising a set of composite blocks, each composite block capable of executing a predetermined set of instructions. A sequencer is included for controlling the set of composite blocks and directing instructions among the set of composite blocks based on a data-flow graph. Further, a data network is included and transmits data to and from the set of composite blocks and to the sequencer, while a status network routes status word data resulting from instruction execution in the set of composite blocks. With the present invention, an effective combination of hardware resources is provided in a manner that provides multi-bit digital signal processing capabilities for an embedded system environment, particularly in an implementation of an adaptive computing engine. These and other advantages will become readily apparent from the following detailed description and accompanying drawings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.