Selection of link and fall-through address using a bit in a branch address for the selection
US6874081B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2001 |
| Grant date | Mar 29, 2005 |
| Priority date | — |
| Expiry date | Apr 16, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3806
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A link address/sequential address generation circuit is provided for generating a link/sequential address. The circuit receives the most significant bits of at least two addresses: a first address of a first set of bytes including a branch instruction and a second address of a second set of bytes contiguous to the first set. The least significant bits of the branch PC (those bits not included in the most significant bits of the addresses received by the circuit) are used to generate the least significant bits of the link/sequential address and to select one of the first address and the second address to supply the most significant bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.