Timing skew compensation technique for parallel data channels
US6874097B1 · kind B1 · utility
50Cited by
4References
45Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 1, 2001 |
| Grant date | Mar 29, 2005 |
| Priority date | — |
| Expiry date | Sep 19, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00104
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for correcting the timing skew of data signals in a parallel data transmission system, such as Small Computer System Interface (SCSI) data bus, relative to a receive clock in the data bus. The system separately corrects the receive clock duty cycle, and also features independent de-skewing of the rising and falling edges of a data waveform to improve timing accuracy of transmitted signals. The method and apparatus can be used without substantial changes to existing transmission system protocols, and can be implemented on an all-digital integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.