Fault tolerant operation of reconfigurable devices utilizing an adjustable system clock
US6874108B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 27, 2002 |
| Grant date | Mar 29, 2005 |
| Priority date | — |
| Expiry date | Oct 23, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17764
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of fault tolerant operation of an adaptive computing system includes identifying a faulty resource in a signal path of the adaptive computing system, reconfiguring the signal path to avoid the faulty resource, estimating a time delay created by reconfiguring the signal path, and adjusting a system clock period to accommodate the time delay. In a preferred embodiment, an FPGA is configured into an initial self-testing area and a working area. Resources located within the self-testing area are tested and faulty resources identified. The FPGA is then reconfigured to avoid the identified faulty resources. When the resources are reconfigured for fault tolerant operation, signal path delays may be introduced into the system. If the signal path delays are in a critical path, a period of a system clock may be adjusted in order to insure proper fault tolerant operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.