Apparatus and method for self testing programmable logic arrays
US6874110B1 · kind B1 · utility
24Cited by
15References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 11, 2000 |
| Grant date | Mar 29, 2005 |
| Priority date | — |
| Expiry date | May 11, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318516
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A self-testing programmable logic array PLA system has an array of programmably interconnected logic cells, a built-in self-test (BIST) structure interconnected with the logic cells, and a BIST engine having an initiation input. The system is characterized in that, upon receiving the initiation input, the BIST engine drives the BIST structure to test connections and functions of the PLA. BIST systems are taught for stand-alone programmable logic arrays (PLAs) and for PLAs embedded in System-on-a-Chip (SoC) devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.